Circuitry within integrated circuit devices typically have a need to be reset by activation of a reset input pin on the device to establish an initial state in the circuitry. Conventional reset operations are based on either an asynchronous reset style whereby the circuitry responds immediately to a reset pin activation or a synchronous reset style whereby the circuitry responds to a reset pin activation after the activation has been timed by a clock signal.
FIG. 1 illustrates a prior art integrated circuit 100 that includes a register 101 and logic 102. The register 101 receives data from bus 103 and outputs data on bus 104. The operation of register 101 is timed by a clock 109. Logic 102 receives input data from bus 104 and outputs data on bus 105. Logic 102 comprises combinational gating, represented by exemplary AND gate 108. The representative gate 108 receives input data from bus 104 and outputs data onto bus 105. The register 101 and logic 102 could be part of any type of digital circuits within the integrated circuit. Examples would include functional elements such as registers, arithmetic logic units (ALU), digital signal processors (DSP) or circuit elements included for test or emulation.
FIG. 1 illustrates a reset input pin 110 providing a reset signal to input buffer 106. The output of the buffer 106 drives the asynchronous reset input terminal 113 of the register 101. In this example, register 110 will be immediately reset in response to a logic low input on the reset pin 110. When register 101 is reset, it outputs a known data pattern to logic 102 via bus 104. Logic 102 responds by outputting a known data pattern on bus 105. FIG. 1 illustrates an example flip-flop 111 which is a part of register 101. Each flip flop 111 of register 101 has an input coupled to bus 103, an output coupled to bus 104, a clock input coupled to clock 109, and an asynchronous reset input coupled to buffer 106 output 112.
A pull up element 107 is connected to the input of buffer 106 to maintain a logical ‘high’ on the reset input pin 110 when it is not externally driven. In this example, pull up element 107 is shown as included on the integrated circuit, but it could be external to the integrated circuit. The pull-up resistor 107 helps prevent false reset inputs. However, noise produced in the system including the integrated circuit may reach sufficient levels to propagate through buffer 106 to cause a false reset of register 101. Further, the operation of the integrated circuit 100 itself can introduce noise on reset line 112, which can also cause false reset inputs to appear at the asynchronous input of register 101. The asynchronous reset approach of FIG. 1 immediately resets register 101 and logic 102, but has the disadvantage of being susceptible to false reset signals.
FIG. 2 illustrates a prior art integrated circuit 200 having a synchronous reset. Register 201 operates functionally the same as register 101 of FIG. 1. Register 201 receives input data from bus 103 and outputs data to bus 104 during the cycle of input clock 109. The difference between register 201 and register 101 is that register 201 includes exemplary flip-flops 203 that do not include the asynchronous reset input of flip-flops 111. The flip-flops 203 include AND gates 204 at their data inputs which input data from bus 103 during functional operation and force a reset input during reset operation. If the reset output 112 from buffer 106 is high, the flip-flops 203 receive normal input data from bus 103 via gate 204. When the reset output 112 is low, the flip-flops 203 are forced by gate 204 to receive input logic zeros. In circuit 200 and in circuit 100 of FIG. 1, this is the ‘reset’ state of registers 201 and 101.
Providing the reset signal as a data input to flip-flops 203, instead of as an asynchronous input to flip-flops 111 lessens the possibility of false resets occurring. However the synchronous reset approach of FIG. 2 delays the effect of the reset until the occurrence of a clock 109 signal.